| 澤豐薄膜陶瓷基板技術(shù)路線 | |||
|---|---|---|---|
| Time | 2022.H2 | 2023.H1 | 2023.H4 |
| Wafer | 14nm | 7nm | 5nm |
| LTCC Substate Size | 150*150mm | 200*200mm | 300*300mm |
| LTCC Satck up | 20Layer | 30Layer | >50Layer |
| LTCC Pad Pitch | 250μm | 150μm | 120μm |
| LTCC Line/Space | 100/100μm | 50/50μm | 30/50μm |
| LTCC Flatness | ≤ 10μm | ≤ 10μm | ≤ 10μm |
| Thin Film Stack up | 1Layer | 3Layer | 6Layer |
| Thin Film Pad Pitch | 85μm | 50μm | 30μm |
| Thin Film Line/Space | 18/25μm | 10/10μm | 5/5μm |
| Probe Card Interposer Specifictions,Top to Bottom | |
|---|---|
| Specification | ZENFOCUS |
| Bump pitch I/O ares or w/b pad pitch | 50um，60um，80um，100um+ |
| Maximum die size or multi-die array size | 100mm X 100mm |
| Type (Interposer) | Organic Build-up with Core & Coreless |
| Material | Normal substrate material |
| # of Build-up layers (per side) | 2~14 (max) |
| # of Core layers | 2~14 (max) |
| Maximum number of separate power leves requiring a plane | depend on Current and Voltage of IC |
| Core via pith | 350um+ |
| Core via diameter | 130um+ |
| Buld-up lines and spaces requirement (include top layer) | 14~20um/14~20um |
| Thickness requirement | 1.0~3.0mm |
| Flatness requirement | < 50um (size 50*50mm or smaller |
| Top layer metallurgy (die side) | Hard Gold or ENEPIG (Au thickness>0.30um) |
| Top layer to die contact type | Needle |
| Bottion layer metallurgy (probe card side) | ENIG or ENEPIG |
| Bottion layer to probe card contact type | Solder (Both Pb & free) |
| Maximum life of interposer,both time and touch-downs | N/A |
層數(shù): 24 層 (10 + 4 + 10)
厚度: 1.4 mm
尺寸: 70 x70 mm
C4 Pitch: 85μm
Site數(shù)量: 8
層數(shù): 10 層 (4 + 2 + 4)
厚度: 1.5 mm
尺寸: 45.48 x18 mm
C4 Pitch: 54μm
Site數(shù)量: 16
